An ADC 10 is shown in FIG. 1. This example ADC is a Successive Approximation Register ADC (SAR-ADC). The ADC input is connected to a track-and-hold unit 11. A comparator 13 compares the input held in the track-and-hold unit 11 with the value output from a Digital-to-Analog Converter (DAC) 12. The comparator output is input to the SAR logic 14, which provides both the ADC output and the input to the DAC 12.
The converter works with the binary search algorithm. First, the input signal is applied and compared with half the scale of the signal reference (thus, the 100 . . . 00). Dependent on the comparison result, the DAC output value is increased or reduced in binary levels to approximate successively the input signal. For a 10 bit (10b) SAR ADC, a minimum of 10 successive cycles is needed. At this point the approximation has finished and the loaded DAC value represents the digitized value of the input signal. The comparator 13 often incorporates internally a pre-amplification stage that amplifies the difference between the signal input and the DAC signal before determining the sign of this difference.
In a particularly popular implementation of SAR ADCs, the DAC is implemented with Switched Capacitors (SC) and is combined with the SAR ADC's re-sampling capacitor. FIG. 2 shows a basic schematic of this approach, in which a plurality of capacitors C1, C2 . . . Cn are switchably connected to the input—that is, they are connected to the input with use of switches, and function both as re-sampling capacitors, and as the DAC. Although many implementations exist, the basic principle remains the same.
One of the advantages of the switch capacitor implementations for the SAR ADC is, by combining the sampling capacitor and the feedback DAC into one capacitor network, area and eventually power can be saved. The operation is as follows: in the sampling phase the bottom plates of all the capacitors are connected to the input signal while switch Sp is closed grounding the top plates. Once the signal is sampled, Sp is opened and all the bottom plates are grounded causing the top plated to become equal to the negative of the sampled input voltage (since charge must be conserved). The conversion proceeds by connecting one by one the bottom plate capacitors having binary weights to a reference voltage Vref. Due to charge redistribution the top plate changes values until step-by-step it eventually comes back to zero. At this moment, the original setting has been restored and the code loaded on the DAC is the digitized equivalent of the input signal.
FIG. 3 shows a time interleaved ADC incorporating SAR ADCs. The signal input is connected to a plurality of track and hold units T/H, each of which is associated with a single SAR ADC unit 32. The outputs from the SAR ADC units are combined in a data recombination unit 33, to produce an output stream. The T/H units are controlled by means of local clock signals 34.
When one incorporates SAR ADC's in a Time-Interleaved ADC as shown in FIG. 3, there are additional constraints being placed on the SAR ADC. Consider for example 16 slow 10-bit SAR ADC's running each at 50 MS/sec. The time-interleaved algorithm would in theory allow an effective rate of 800 MS/sec. Because the slow SAR ADC's have limited input bandwidth for sampling (e.g. 25 MHz), additional dedicated (high-speed) track-and-hold circuits (T/H) are needed (often, but not always, one T/H per SAR ADC) to provide to each SAR ADC unit a well-settled signal. The SAR ADC incorporates its dedicated means to re-sample this signal (as in FIG. 3) and proceed further with the conversion.
Because all SAR ADC's process the same input signal, the distribution of the input signal from the input source via the high-speed T/H to each individual SAR ADC inputs creates a significant interconnection wire overhead, leading to bandwidth limitations. It can also create different signal delays from one SAR ADC unit to the other, which reflect to performance degradation. Capacitive loading of the SAR ADC input stages reduce the input bandwidth even further.
To overcome the bandwidth limitations, the high speed T/H usually incorporates a dedicated source follower, or buffer, or more generally an amplifier circuit with gain A that is higher or lower than unity. This is shown in FIG. 4. In FIG. 4, the input is directed to each of a plurality of T/H units 11. Between each T/H unit 11 and its associated SAR ADC (having its own DAC 12, comparator 13 and SAR logic 14) is connected a buffer or follower 45. The buffer or follower 45 reduces effectively the capacitive loading between the high speed T/H and the far-away placed SAR ADC, and makes any capacitive differences in the paths between high-speed T/Hs and unit SAR ADCs (the capacitors C shown in FIG. 4) less significant, as regards the ADCs overall accuracy.
This amplifier (or buffer or follower) improves significantly the conversion but in return causes non-linear distortion to the signal; the DAC feedback signal is now compared to a signal that is distorted by the compressive behavior of the amplifier. The distortion becomes higher for large input signals, and significantly more important for high-resolution levels.
The problem just described becomes a performance-limiting factor in modern submicron CMOS processes (e.g. 65 nm) with low supply voltages. It becomes increasingly difficult in these processes to realize such buffers that offer broad signal bandwidth (e.g. GHz), very high linearity (e.g. Total-Harmonic-Distortion of −60 dB, or less) and high signal swing (e.g. 0.5-1V), the last being required to reduce the noise impact on the signal quality.
Although this problem can be addressed by means of optimizing the circuit topology of the amplifier/buffer circuit for the combination of linearity, bandwidth, voltage swing and power consumption, there remains an ongoing need for an ADC which is able to at least to some extent reduce or ameliorate the problem of distortion in the amplifier, buffer, or follower.